A major concern of memory cells having a split gate (or stacked gate) structure arranged in a memory array is with the over-erase problem when operating a particular memory cell or cells in the memory array. Memory cells having the split gate structure arranged in a memory array avoids the over-erase problem by adding select gate (SG) and control gate (CG) in series with the floating gate (FG). However, it is difficult to scale down the split gate structure using prior art technology because in the prior art, the select gate and the control gate is not self-aligned to the floating gate. Consequently, the cell size of the split gate structure is generally larger than the stacked gate structure in order to provide for problems associated with misalignment of the gates. Furthermore, misalignment of the respective drain and source regions of adjacent memory cells also cause program mismatch and sub-threshold disturbance.
It would be desirable to have a method for manufacturing memory cells arranged in a memory array that is scaleable, can be fabricated using self alignment techniques, and have a resulting memory array that requires low current for programming the memory cells.